1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly to a dynamic random access memory device (DRAM) having a triple-well structure and which is capable of suppressing the body effect for transistors formed on a heavily doped substrate or well region. The triple-well structure is used to improve the isolation properties of transistors formed therewithin.
2. Description of the Related Art
In a semiconductor memory device such as a DRAM, in order to reduce the junction capacitance of a transistor and to improve isolation characteristics of peripheral devices and operating characteristics of a transistor, a negative voltage is supplied to a substrate or a well.
However, an increasing integrated circuit density results in the length of the transistor channel being shortened and the effective threshold voltage being lowered.
In order to protect against short channel effects, a heavily doped substrate or well is commonly used in highly integrated semiconductor memory devices.
If the absolute value of a negative backgate voltage V.sub.BB applied to the substrate or well region increases, the threshold voltage of the transistor formed therein rises resulting in a large body effect.
A 16 Mb DRAM produced by TOSHIBA Co. appears to overcome the effect of large threshold voltages by using a triple-well structure consisting of one N-type well and two P-type wells.
This TOSHIBA triple well-structure is different from conventional layouts having a twin-well structure consisting of one N-type well and one P-type well. Such a triple-well structure is disclosed in an article by Fujii et al, entitled "A 45 ns 16 Mb DRAM with Triple-Well Structure", ISSCC Digest of Technical Papers, Feb. 17, 1989, pp. 248-249.
FIG. 1 illustrates the TOSHIBA triple-well structure discussed above. As shown, N-type substrate 11 is used to simplify the fabrication process with an N-type well 13 and first and second P-type wells 12 and 14 formed therein.
A PMOS transistor 16 constituting a peripheral circuit portion and a memory cell array portion is formed in the N-type well 13.
A well bias voltage (or a backgate voltage) from power supply voltage Vcc is applied to N+ region 21 in N-type well 13 and to P+ region 22 of the PMOS transistor 16.
The NMOS transistor 15 constituting the peripheral circuit portion is formed in the first P-type well 12. Because a well bias voltage of ground voltage level Vss is applied to P+ region 23 within first P-type well 12, a large body effect can be suppressed. Thus, any upward change in the effective threshold voltage of the NMOS transistor 15 is foregone.
A memory cell array portion comprising the NMOS transistor 17 and an associated capacitor is formed in the second P-type well 14.
A well bias voltage of negative backgate voltage level V.sub.BB is applied to the P+ ion implanted region 24 in the second P-type well 14 as shown in FIG. 1. As a result, data retention and transistor isolation characteristics are improved.
However, because the NMOS transistor 15, associated with the peripheral circuit portion of the memory device, is formed in the first P-type well 12 in which a ground voltage level Vss corresponding to the well bias voltage is applied, the junction capacitance of the NMOS transistor 15 is increased.
Hence, the operating speed of the peripheral circuit portion is reduced and the isolation characteristics are deteriorated.
Consequently, the distance between transistors along the peripheral circuit portion of the memory device must be enlarged resulting in the chip layout area becoming increased.
Furthermore, because a well bias voltage of ground voltage level Vss is applied, the respective transistor threshold voltages vary and a latch-up phenomenon resulting from noise in the ground voltage are liable to be generated.
In addition, the use of an N-type substrate requires that an N-type well be formed having a deep junction along an input/output pad. This is very difficult to achieve particularly when this portion of the chip is to be used as an input protection device.
FIG. 2 illustrates another conventional triple-well structure. The use of P-type substrate 31 for the substrate of the device of FIG. 1 is found to more easily facilitate the formation and use of the chip as an input protection device.
However, because the first P-type well 32 formed along a peripheral circuit portion of the chip has the same construction as the first P-type well 12 of FIG. 1, the operating speed remains slow and the chip layout area is increased.
Moreover, variations in threshold voltage and the latch-up phenomenon are similarly engendered as in the chip layout of FIG. 1.
The second P-type well 35 having a high impurity concentration is formed in the N-type well 34 and a well bias voltage of negative voltage level V.sub.BB is applied thereto.
In the high impurity concentration well 35, as the absolute value of the applied negative voltage increases, the transistor threshold voltage increases as well due to the body effect.
Generally, the degree of increase in transistor the threshold voltage varies depending on the state of data ("1" or "0") stored in the corresponding memory cell area.
In addition, during the chip fabrication process, because the corresponding memory cell area is formed in a twin-well consisting of N-type well 34 and second P-type well 35, silicon crystal defects may occur which deteriorate memory cell data retention capacity.